After delving into Texas Instrument’s crystal-replacing bulk acoustic wave (BAW) oscillator recently, Electronics Weekly is taking a look at an advanced version of the humble RC oscillator, reported at the International Solid State Circuits Conference earlier this year (ISSCC 2020).

The work of Delft University of Technology, the 180nm CMOS oscillator has been given so much digital enhancement that, after a digital two-point trim, it can produce 16MHz with ±400ppm inaccuracy across -45°C to 85°C.

It relies on two networks:

An RCCR Wien bridge (WB in diagram) using metal-insulator-metal capacitors and p-poly resistors for minimum temperature deviation. This is the time-keeper of the master oscillator.
A potentiometer (WhB for Wheatstone bridge in diagram) with a parallel pair of p-poly resistor at the bottom and a silicided-diffusion resistor at the top. This last resistor is chosen for its high temperature dependence, and this network is used to temperature-compensate the Wien bridge.

The Wien bridge is a phase-shift network, built into a frequency-locked-loop using a phase domain ΣΔ modulator to turn it into a digitally-controlled oscillator running at the centre frequency of the network.

In the potentiometer, one of the two parallel lower p-poly resistors has a series switch that can open-circuit it – turning the pot into a form of 1bit DAC.

Building this simple DAC into the loop (loop connection not shown in diagram) of a continuous-time ΣΔ modulator, creates an ADC whose output bit-stream average represents the ratio of potentiometer resistors, which is a function of temperature, but independent of driving frequency.

Through the choice of resistor and capacitor materials, the temperature dependencies of Wien bridge and Wheatstone exhibit similar non-linearities, and it is this that allows high accuracy to be achieved with only a two-point trim (at -35°C and 75°C).

Compensation is through a first-order polynomial that generates a compensating phase within the Wien bridge oscillator loop.

There is more going on here: for example both bit streams are decimated by digital filters to cut the loop sample rate to ~500Hz, and the digital DCO has course-fine tuning that give it ~30ppm resolution, while allowing it to reach across a broad (±40%) batch-to-batch process spread.

Resulting quantisation noise floor appears to be ~30ppm (1.8ps jitter) and supply sensitivity is 0.12%/V over 1.6 – 2V. Power is 400μW and footprint around 0.3mm2.

ISSCC 2020 paper 3.4 ‘A 16MHz CMOS RC frequency reference with ±400ppm inaccuracy from -45°C to 85°C after digital linear temperature compensation’.