Demand for thinned wafers will grow at a 5% CAGR from 2019-2025,  says Yole Développement, to reach more than 135 million thinned wafers at the end of the period.

The market is mainly pushed by memory, CIS and power SiC components as well as LED and laser diodes.

The thinning equipment market is dominated by the two major grinding & CMP equipment suppliers, DISCO, ACCRETECH. They are followed by Revasum and Ebara.

“The demand for thinned wafers continues to increase owing to miniaturization associated with greater performance driven by a wide range of applications, such as stacked packages within mobile devices and other consumer products,” says Yole’s Amandine Pizzagalli .

In parallel, Yole predicts a 10% CAGR during the same period for the overall thinning equipment market.

According Yole’s semiconductor manufacturing team, this industry was worth almost $461 million in 2019 and will exceed almost$792 million by 2025 mainly generated by memory, CIS and power SiC components as well as LED and laser diodes.

Most semiconductor wafers are thinned down to a range of 100 µm-200 µm especially when it comes to memory, CIS and power applications.

However, some silicon wafers are thinned down well below 100 µm in HVM , including some 3D stacked memory devices, CIS and power devices.

The total memory architecture thickness varies typically from 50 µm to 400 µm depending on the manufacturer and the packaging technology.

For instance, standard memory, like DRAM or 2D NAND, uses silicon wafers that are thicker than 200 µm, while 3D stacked DRAM keeps moving downward, from 50 µm to 30 µm thick silicon substrates by 2025.

Incidentally, the 30 µm to 50 µm thickness range is the one in which the largest number of thinned wafers is expected by 2025.

Meanwhile, BSI CIS wafers are thinned down below 10 µm thickness and are today the thinnest wafers across all semiconductor applications.

“The thickness of power devices depends on applied voltage as well as semiconductor substrate type,” says Pizzagalli, “from a wafer substrate point of view, Si-based MOSFETs involve wafer thickness of around 50 µm to 55 µm on 300 mm diameter wafers in HVM with a trend towards thinning down to 30 µm. Wafer thicknesses for SiC-based devices are rarely lower than 200 µm even though thickness reduction is expected to go down to 100 µm/110 µm in the next few years.”

In parallel, typical wafer thickness for MEMS sensors is today in a range of 200 µm to 350 µm, especially for inertial MEMS.

At the end, RF wafers devices are in the range of 140 µm and 200 µm and are opposite to every other the semiconductor devices in terms of thickness reduction.

RF device wafers are getting thicker, with the thickness depending on whether wire bonding or flip-chip packaging will be more widely adopted by the industry.

At the back-end wafer stage, thinning methods are employed for thinning down the wafers and sometimes even removing the substrate, for LEDs on silicon for example.

Although there are similar and common drivers for thinning’s applicability in semiconductor applications, the reasons for using such techniques differ from one device to another and depend on the end-applications.

The microLED market, should it take off and should it use back thinning technologies, could give a significant boost both to wafer-starts and to the corresponding equipment market.

The same can be said for CIS, 3D sensing applications or a widespread shift to SiP technology. As of today and in the case of MEMS devices, such components are typically composed of a stack of a sensor element wafer, a cap and an ASIC.

All three wafers must be thinned to reduce the size of the device. With respect to power devices, thin wafers are needed here since reduced thickness lowers on resistance, improves current carrying capability and minimizes power consumption.

On the other hand, CMOS image sensor wafers are thinned down for TSV packaging where thinning is needed to achieve a very small form factor. BSI with extreme thinning below 10 µm enhances light sensitivity, while hybrid stack and triple stack architectures are pushing the boundaries further.

Traditional LED fabrication also requires a thinning or a removal step at the back-end for miniaturization and easier dicing/singulation.

Laser diode requirements are much less stringent but the emergence of high-power VCSELs demands much thinner wafers for enhanced heat management. In the case of memory devices, further thickness reduction is driven by the need to maximize memory capacity of single packages, improved data transfer rates as well as power consumption mostly fueled by mobile applications.