CEA-Leti scientists have made FDSOI CMOS at 500°C, “while showing strong performance gains especially in p-type MOS logic devices”, according to the French lab, which has branded the process ‘CoolCube’.

500°C processing is important when trying to shrink die by building CMOS with p-channel mosfets above rather than next to their n-channel counterparts – called a ‘3D sequential’ structure.

If too much heat is used to build the second layer of transistors, the metal interconnect and silicide of the bottom-level transistors is damaged.

The work, done with Samsung, was presented last week at the virtual 2020 Symposia on VLSI Technology & Circuits.

According to the presentation:

3D sequential integration becomes more and more attractive for More Moore and More than Moore applications.

One of the main advantages of this 3D technology, versus die-to-die for instance, is the major gain of density brought by the nm-scale lithographic alignment between the two levels.

The maximum temperature regarding bottom device’s silicide integrity and inter-tier interconnections preserved reliability should not exceed 500°C for a couple of hours. Several low-temperature devices have been published in literature, but up to our knowledge, this is the first proof-of-integration of CMOS devices processed at a temperature of 500°C, compatible with advanced FDSOI platforms.”

The lab also demonstrated two standard process-proving circuits: 500°C ring oscillators and SRAM bit-cells.

Applications are expected in logic, RF, in-memory computing, AI, imaging and display applications.

The paper is called ‘First demonstration of low temperature (≤500°C) CMOS devices featuring functional RO and SRAM bitcells toward 3D VLSI integration’.