TSMC is “preparing for a fast and steep recovery,” said Maria Marced president of TSMC Europe (pictured) at the company’s virtual symposium this morning.

Although the IMF is predicting a 4.9% fall in world GDP this year, the semiconductor industry is expected to be flat or slightly up,  pointed out Marced, while customers are showing a thirst for innovative products and new processes.

Marced pointed to a number of significant customer innovations including Bristol’s Graphcore which has delivered the world’s most complex processor containing 59.4 billion transistors made on TSMC’s 7nm process.

“TSMC and Graphcore are looking at the advantages to be gained from the 3nm process,” said Marced.

At 16nm Graphcore’s first chip contained 24 billion transistors, at 7nm its chip had 59 billion transistors so, at 3nm, it could be looking at 100 billion+ transistors.

Volume production on 3nm is projected for H2 2022.

TSMC CEO C C Wei (pictured) said that Fab 18  – “the most advanced fab on the planet” –  entered volume production on 5nm in Q2 2020.

Wei said the fab took eight months to build and is TSMC’s fourth Gigafab.

Next year, in Q4, the 5nm process will be refined to a node designated N4 and, in 2022, volume production on 3nm begins.

Wei reiterated the TSMC approach to business: “Customer trust is one of our core values,” he said, “we have never competed with our customers.We have never had our own products.”

Y J Mii, svp R&D, said that TSMC had received 140 customer tape-outs on 7nm and expected 200 by the end of the year.

Mii said that the N7+ process was the world’s first use of EUV in volume production.

A refinement to the node, N6, has an 18% density improvement over N7.

N5 is 15% faster, with 30% less power and a 1.8x density improvement over N7.

The N5P process delivers an additional 5% speed improvement and a 10% power improvement. 

N4 starts risk production in Q4 2021 and volume production in 2022.

N3, the 3nm process, has a 10-15% speed improvement at the same power or a power reduction of 25-30% at the same speed, with a logic density improvement of 1.7x, an SRAM density improvement of 1.2x and an analogue density improvement of 1.1x.

Risk production on N3 starts in 2021 with volume production in H2 2022.

New materials and transistor structures include a 32Mb nanosheet SRAM which had been made with a good yield and a BEOL CNT power gating device integrated with silicon CMOS.

YP Chin, svp operations, told the symposium that TSMC is growing capacity at a rate of 28% CAGR. 

He said that 5nm capacity, which began volume production in Q2, would triple by 2022.

Chin added that TSMC now owns 50% of the world’s installed EUV capacity.

Chin added that the company’s 2nm fab would be built at its original site – Hsinchu – on land already acquired by TSMC.