Author: EIS Release Date: Oct 12, 2020
iWave’s has created a development platform around Xilinx Zynq Ultrascale+ ICs that supports HDMI 2.0 at up to 18Gbit/s and video resolutions up to 4K at 60Hz.
iWave-HDMI2-dev-board
“The emergence of HDMI 2.0 and the widespread acceptance of this technology is making a deep impact on the multimedia and entertainment industry,” according to iWave, “The urge to support high-speed data transmission and ongoing advancements has made industries to focus on providing a diverse category of products that can support all necessary logic to deliver HDMI functionality.
The system-on-module at the heart of the hardware has a 1.5GHz quad-core Arm Cortex-A53, 600MHz dual-core Cortex-R5 real-time processor, a Mali 400MP2 GPU and up to a million logic elements.
On-board is 4Gbyte of DDR4 RAM with error-correcting code for the processors, dual 4Gbyte DDR4 for the programmable logic, 8Gbyte eMMC flash (expandable to 128Gbyte) for storing videos and support for 12G SDI in/out, HDMI 2.0 in/out and SATA for extended storage via the M.2 expansion slot.
Peripherals include 10G Ethernet, QSFP, FMC and FMC+ via IBERT design transceiver loopback, PMOD I/Os, SFP+ via IBERT design from programmable logic and 10/100/1000Mbps Ethernet support via GEM0 and GEM3, standard SD connector via SD1, USB2.0, CAN0, I2C0, UART0 as debug, USB3.0 via PS GTR, UART, UART1, PS JTAG, PCIe as the root port.
“To help users to create video solutions with HDMI interfaces, the platform is incorporated with pre-packaged sub-systems for HDMI transmission and reception,” said IWave. “The HDMI 2.0 TX subsystem is hierarchically packed for easy configuration in Vivado integrated design environment interface to create required hardware accordingly. With integrated modules such as video timing controller and AXI4-Stream to video out bridge, allows the HDMI 2.0 TX subsystem to support AXI4 Stream-based video input for other Xilinx video processing IP cores.”
AXI4-Stream here supports dual-pixel per clock with 8 bits, 10 bits, 12 bits or 16 bits per component for RGB, YUV colour spaces.
The subsystem allows the end-user to build an HDMI source device that negotiates with the HDMI sink device for supported features and capabilities.
Communication between the source device or devices and the sink device is implemented through the Display Data Channel (DDC) lines, which is an I2C bus included on the HDMI cable.
There is a board support package for HDMI input and HDMI output that includes FPGA design and software packages.