Imperas’ riscvOVPsim RISC-V reference model and simulator has been updated and extended for RISC-V vector instructions and now supports coverage driven verification analysis.

The base version of riscvOVPsim is available for free from a new GitHub site  (github.com/riscv-ovpsim), with an enhanced version including an extensive RISC-V vector test suite also freely availablewith an enhanced version including an extensive RISC-V vector test suite also freely available for commercial use from Open Virtual Platforms (OVPworld.org/riscv-ovpsim).

The upcoming ratification of the RISC-V Vector instruction extension offers system designers broad flexibility to configure vector engines to support complex arithmetic operations required for applications involving linear algebra, such HPC (High-Performance ), AI (Artificial Intelligence) and ML (Machine Learning) applications.

With these enhancements to riscvOVPsim, software developers and system architects can start to explore RISC-V based solutions, while Design Verification (DV) Engineers can configure the models for test benches and test frameworks with coverage analysis.

The open standard ISA (Instruction Set Architecture) of RISC-V offers processor designers many options and configuration possibilities and across the RISC-V ecosystem the efficient description of these parameters is becoming more important as part of the verification, compliance, tools and software support for RISC-V.

The riscvOVPsim simulator includes an envelope model that supports all the RISC-V ratified specification options, which can be easily configured to match targeted processor features as a key step in setting up a verification test bench. riscvOVPsim has also been updated with coverage features that easily and efficiently support instruction functional coverage-based verification flows.

Since Imperas first launched riscvOVPsim to support the RISC-V International compliance working group in 2018, it has become widely adopted by both open source and commercial processor development teams looking for a dependable RISC-V reference model that can be easily configured and is the key reference within their compliance, directed and random test generation environments and frameworks.

The Imperas support for the RISC-V vector instruction extension also includes a new architectural validation test suite which features detailed instruction tests for a base vector engine configured as RV32GCV with elen:32, vlen:256, slen:256.

The vector suite is built by the Imperas directed test generator and includes over 3 million instructions in 5-7,000 test files (depending on suite configuration), with full source, assertions, and reference signatures. (More details here: https://github.com/riscv-ovpsim/imperas-riscv-tests/tree/main/riscv-test-suite.)

The tests currently achieve over 85% instruction functional coverage which will approach 100% when the vector instruction extensions are ratified by RISC-V International. The test suite can be generated for any of the recent published draft specifications (including 0.8, 0.9, 1.0draft) and compliant vector engine configurations including enhanced options such as use of BFloat16 for floating point optimized for accelerating machine learning and near-sensor computing applications.

The new enhanced simulator and new test suites are freely available with many processor, behavioral, and virtual platform models, with various SystemVerilog examples and test benches for Hardware Design Verification and other community resources from Open Virtual Platforms at OVPworld.org/riscv/.