Imperas has extended its Risc-V reference model and simulator to cover forthcoming vector instructions and to support coverage-driven verification analysis.

Imperas-riscvOVPsim_vectors

Called riscvOVPsim, the enhanced version including a vector test suite is freely available for commercial use from Open Virtual Platforms, and a base version is available free from GitHub.

“The upcoming ratification of the Risc-V vector instruction extension offers system designers flexibility to configure vector engines to support complex arithmetic operations required for applications involving linear algebra, such high-performance computing, AI and machine learning applications,” according to the company. “With these latest enhancements to riscvOVPsim, software developers and system architects can start to explore Risc-V based solutions, while design verification engineers can configure the models for test benches and test frameworks with coverage analysis.”

riscvOVPsim simulator includes an envelope model that supports Risc-V ratified specification options, which can be configured to match targeted processor features as a key step in setting up a verification test bench.

riscvOVPsim has also been updated with coverage features that support instruction functional coverage-based verification flows.

“Since Imperas first launched riscvOVPsim to support the RISC-V International compliance working group in 2018, it has become widely adopted by both open source and commercial processor development teams looking for a dependable RISC-V reference model that can be configured and is the key reference within their compliance, directed and random test generation environments and frameworks,” claimed the company.

Imperas support for Risc-V vector instruction extension includes a new architectural validation test suite which features instruction tests for a base vector engine configured as RV32GCV with elen:32, vlen:256, slen:256. The vector suite is built by the Imperas directed test generator and includes >3 million instructions in 5-7,000 test files, depending on suite configuration, with full source, assertions, and reference signatures.

“The tests currently achieve over 85% instruction functional coverage which will approach 100% when the vector instruction extensions are ratified by Risc-V International,” said Imperas.

The test suite can be generated for any of the recent published draft specifications including 0.8, 0.9, 1.0draft) and compliant vector engine configurations including enhanced options such as use of BFloat16 for floating point optimised for accelerating machine learning and near-sensor computing applications.

Enhanced riscvOVPsim including the vector test suite is available on OVPworld.