IGaN of Singapore is claiming lower losses from its 150mm RF GaN-on-silicon epi wafers.

IGaN-rf-GaN-on-Si-HEMT-losses

“Despite the great promise showcased by GaN-on-Si RF electronics, there remain few issues to be resolved,” according to company technologist Dr Karthikeyan S. “One such issue is the presence of parasitic channel formed at III-nitride/silicon interface, which leads to parasitic loss, degrading output power, power gain and efficiency of devices especially when they are operating at high frequency.”

Building a GaN-on-Si wafer requires a stack of intermediate material layers, such as aluminium nitride, between the silicon wafer and the GaN active layers to accommodate physical differences between the materials, including lattice constant and thermal expansion mismatches.

Without a good stack, the wafer can bow or crack, and GaN crystal quality can be compromised.

“A key requirement is the reduction of conduction loss at the AlN/Si interface,” said Karthikeyan. “As the AlN/Si interface can become conductive due to the doping of Al and Ga residuals in the reactor, preconditioning of the reactor and the growth conditions of first AlN layers on Si substrate will be crucial for the suppression of the conduction loss.”

The company, said Karthikeyan, is achieving low conduction loss in a 150mm RF GaN-on-Si epi stack that it will be offering to customers on 200mm substrates before the end of Q1 2021.

He is claiming 10GHz conduction loss of 0.15dB at room temperature and 0.23dB at high temperature from its 150mm development wafers – see diagram.

“Besides the conduction loss test,” added Karthikeyan, “IGaN has implemented a quick method of screening-out poor-performing GaN epiwafers before fab processing, that can save customers scrappage and help avert wastage of processed wafers and packaged devices downstream if the epiwafer substrates has high conduction losses.”

The company IGaN is also known as IGSS GaN.