Marvell claims to be first to deliver a 112G 5nm SerDes design that has been validated in hardware.

Marvell says it has a customer which  will embed the IP to build next generation top-of-rack (ToR) and spine switches for  hyperscale data centers around the world.

Marvell’s 5nm SerDes claims to double the bandwidth of current systems based on 56G while enabling the deployment of 112G I/Os in many exciting new applications, including network and data center switching, network traffic management, machine learning training and inference, and application-specific accelerators.

The SerDes is claimed to operate at 112G PAM4 across channels with >40dB insertion loss, providing margin that is critical for high reliability infrastructure applications.

The IP also delivers power reduction of more than 25% compared to 7nm, enabling systems with tight thermal/power constraints and helping to drive down total cost of ownership.

The power reduction of Marvell’s high-speed SerDes enables scale up of bandwidth within acutely constrained 5G applications.

Marvell will offer a complete product suite of PHYs, switches, data processor units (DPUs), custom server processors, controllers, accelerators and custom ASICs in 5nm, delivering end-to- end interoperable infrastructure solutions.