SiFive approves Imperas Risc-V simulation models

Author: EIS Release Date: Jul 8, 2021

Risc-V intellectual property creator SiFive has qualified models for its core portfolio from Oxford-based Imperas Software – as well as signing a distribution deal with Valtrix.

 

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Imperas’ models for SiFive processor IP are an instruction accurate programmer’s representation with full functionality including user, privileged, system and debug modes, plus configuration options for Risc-V vector extensions and custom instructions.

 

“The models deliver simulation of 100s to 1,000s of Mips on a modestly configured host PC,” according to Imperas. “As an example, the virtual platform model of the Freedom U540 SoC with five CPU cores boots SMP Linux in under 10s.”

The models couple with Imperas’ debug and analysis tools which support multi-core design tasks including OS porting and abstractions for application development.

 

In addition, the company’s simulator, with proprietary code-morphing, can be integrated within other EDA environments such as SystemC, SystemVerilog, and simulation-emulation tools from Cadence, Siemens and Synopsys, plus Metrics Technologies’ cloud-based offering.

 

“The design freedoms of Risc-V and vector extensions are changing the traditional boundaries between the software and hardware phases of SoC development,” said SiFive v-p product marketing Chris Jones. “The Imperas models help developers with SoC architectural exploration across the full flexibility of the SiFive Core IP Portfolio, and support early software development, which is a critical factor in validating new AI solutions.”

 

“SiFive Core IP portfolio covers the spectrum of the Risc-V ISA, from embedded controllers to multiprocessors supporting SMP Linux, plus the latest vector-based accelerators,” said Imperas CEO Simon Davidmann. “These are the starting points for the next generation of domain-specific devices across almost all market segments and applications.”