Cadence and Tower release RF SOI process

Author: EIS Release Date: Aug 23, 2021

Cadence and Tower Semiconductor  have released a silicon-validated SP4T RF SOI switch reference design flow using the Cadence Virtuoso Design Platform and RF Solution.

 

 

The reference design flow provides a faster path to design closure for advanced 5G wireless, wireline infrastructure, and automotive IC product development.

 

This new RF reference design flow leverages a comprehensive set of mixed-signal and RF design, simulation, system analysis and signoff tools that are tuned for Tower’s CMOS, BiCMOS, SOI and Silicon Germanium (SiGe) process technologies. Using the new offering, joint customers can accelerate RF, mmWave and high-performance analog designs and increase signoff confidence.

 

 

Tower’s RF and high-performance analog design enablement solutions, PDKs and reference flows complement its best-in-class foundry wireless and wireline process technologies, including the CS18 and TPS65RS for RF-SOI and SBC18 for SiGe BiCMOS. RF and mmWave IC and package co-design has been a critical issue for Tower’s customers, and they are now armed with silicon-validated tools and flows. Joint customers can design differentiated ICs optimized for cost and performance.

 

 

 

As frequencies move higher, the need for accurately incorporating multiphysics effects grows. As such, the RF and mmWave PDKs available from Tower now incorporate the Cadence Celsius Thermal Solver, EMX Planar 3D Solver and Clarity

3D Solver technologies to seamlessly account for electromagnetic (EM) and thermal integrity of the design.

 

The multiphysics analysis products complement the existing Cadence toolset in use at Tower, including the Virtuoso environment, Spectre Simulation Platform, Quantus Extraction Solution, integrated Litho Physical Analyzer, and Innovus Implementation System.