Imagination offers Risc-V core IP
Author: EIS Release Date: Dec 13, 2021
Imagination Technologies has announced Risc-V CPU intellectual property for SoC companies.
Imagination Catapult RISC-V CPU block
Branded Catapult, it is a “product line designed from the ground-up for next-generation heterogeneous compute needs,” according to Imagination. “Leveraging Imagination’s 20 years of experience in delivering complex IP solutions, Catapult CPUs can be configured for performance, efficiency or balanced profiles.”
There will be four families:
dynamic microcontrollers
real-time embedded CPUs
high-performance application CPUs
functionally safe automotive CPUs
“The first family, microcontrollers, are already shipping in automotive GPUs in SoCs from Imagination customers,” said the company. “Real-time embedded CPUs are available now. high-performance application CPUs and automotive CPUs will follow from 2022.”
Imagination’s Catapult Risc-V roadmap
The cores are multi-threaded, come in both 32bit and 64bit variants, and have customer-configurable options. Scaling will be up to eight asymmetric coherent cores per cluster, with an option to add custom accelerators.
“There is an ever-greater challenge to process immense amounts of data in tightly constrained area and power budgets,” said Imagination chief of innovation Tim Mamtora. “Heterogeneous architectures are key to providing performance, flexibility and resilience when accelerating an increasingly diverse set of workloads.”
The automotive CPUs are being developed to ISO 26262 automotive standards, according to the company, and will provide “a range of CPU solutions for each ASIL [automotive safety integrity level]”. ISO/SAE 21434 end-to-end security will also be a feature of some cores.
The associated SDK (software design kit) includes enhanced versions of debug tools such as GCC, LLVM and GDB, optimised C libraries, said the company, and an IDE (integrated development environment) called Catapult Studio has been based on Visual Studio Code.
Catapult SDK is available for Windows, Ubuntu, CentOS and MacOS, and includes both FreeRTOS and support for Linux including reference bootloaders, kernels and Yocto-based filesystems.
Catapult CPUs are delivered with both fast and performance models, which offer interactive debug and are compatible with the gem5 simulator for power and energy-efficiency testing.
Open source Risc-V?
The open-source part of Risc-V is the set of related instruction sets – called ‘ISAs’ – available in several 32 and 64bit forms that can be used without paying a licence fee – whereas using most Arm instruction sets does require payment.
Adopters of the ISAs can already rely on Risc-V-specific design tools from third-party suppliers, and other products and services from the growing ecosystem.
These Risc-V ISAs have to be turned into an HDL (hardware description language) design to create a CPU that can be built in silicon, and this is what Imagination is doing – it is an established GPU design house with CPU design experience and CPU patents. For example, it owned the MIPS CPU designs for a few years.
Despite the free instruction set, SoC companies pay for these HDL designs.
Other intellectual property companies including SiFive and Andes are doing something similar, each adding their own secret sauce to Risc-V core designs to improve throughput, power consumption or footprint metrics, for example.
Attracted by zero licence fees and readily-available tools, further companies are rolling their own Risc-V CPUs around the instruction sets for internal use.
“Imagination Catapult CPUs are an exciting new alternative for the Risc-V market,” said Imagination v-p of compute Shreyas Derashri. “They contain all our experience and knowledge in creating innovative silicon IP – Catapult offers comprehensive IP protection, thanks to a portfolio of CPU patents.”