Mentor is addressing the functional safety requirements of ICs in autonomous vehicles with an initiative called ‘Tessent Safety Ecosystem’ which links the firm’s own functional safety tools, including those acquired when it bought Austemper, to those from external partners – notably Arm through its Functional Safety Partnership Program.

At the same time, it announced a related tool – for adding fast test-while-operating hardware for SoCs, called Tessent LogicBIST with Observation Scan technology (LBIST-OST) which operates ten times faster than the firms previous offering, it said, adding that Renesas has already tried it. According to Renesas design director Hideyuki Okabe: “Leveraging the Observation Scan technology featured in the LBIST-OST solution, we were able to reduce the test time for in-system logic built-in self-test by 5x. This enabled us to reduce our fault tolerant time interval [FTTI] when using Logic BIST as a safety mechanism and improve the safety response when detecting new defects in our automotive products.”

On the ecosystem, Mentor marketing director Brady Ben said: “Fast in-system IC test performance is essential to reducing the time between fault detection and engagement of on-chip safety mechanisms. To speed IC test performance, automotive IC designers increasingly need all on-chip safety mechanisms, including DFT and non-DFT technologies, to be closely coupled – and this approach is fundamental to Mentor’s Tessent Safety ecosystem.”

Tessent Safety Ecosystem includes:

• Mentor’s built-in self-test (BIST) technologies including LBIST-OST.
• Tessent MemoryBIST – automation flow that provides design rule checking, test planning, integration, and verification at either the RTL or gate level. BIST and self-repair capabilities can be added to individual cores as well as at the top level.
• Tessent MissionMode – a combination of automation and on-chip IP for enabling semiconductor chips throughout an automotive electronics system to be tested and diagnosed at any point during a vehicle’s functional operation.
• Tessent DefectSim – transistor-level defect simulator for analogue, mixed-signal and non-scan digital circuits.
• Tessent DefectSim – measures defect coverage and tolerance.
• Mentor’s participation in Arm’s Functional Safety Partnership Program – built around Arm safety-ready intellectual property – the Cortex-R52 for example, which combines real-time execution, functional safety and a virtualisation to enable a hypervisor to protect safety-critical code.
• Mentor’s automotive-grade automatic test pattern generation which detects defects at transistor and interconnect levels.
• Links to Austemper SafetyScope and KaleidoScope products, which add safety analysis, auto-correction and fault simulation technology to address random hardware faults- this analyses RTL for faults and vulnerabilities “and is capable of smart fault injection to help safety mechanisms react in a planned manner for covered faults”, according to Mentor.

The functional safety ecosystem was announced at the International Test Conference in Washington this week.

Hierarchical design-for-test automation

Also at ITC 2019, Mentor announced a hierarchical design-for-test (DFT) automation methodology for ICs, called Tessent Connect, as well as an associated quick-start programme, offering detailed flow assessments from Mentor’s applications and consulting services engineers.

“Retrofitting existing flows and automation to use hierarchical components and technologies is often time-consuming and expensive, according to Mentor. “With Tessent Connect, IC designers interact with the Tessent software design tools using a higher level of abstraction, which describes the intended result rather than step-by-step instructions. The benefits of this abstraction-based approach include seamless collaboration across disparate DFT teams, plug-and-play reuse of IC components and the automation of many time-consuming set-up, connectivity and pattern generation tasks.”