Packaging lead time 50+ weeks

Author: EIS Release Date: Apr 18, 2022

Packaging lead times have risen to 50 weeks and more, says Sondrel.

 

In the initial stages of the pandemic, packaging houses were badly hit by cancellation of orders and had to lay off staff or even close down, says Sondrel.

 

As silicon production surges, they are struggling to cope with the result that the lead time for packaging has increased from 8-9 weeks to as much as 50 weeks or more.

 

“The sequence of booking the stages in the supply chain has completely changed,” says Sondrel’s Alaa Alani, “previously, the design would be finished and then sent off to be made into wafers, which still takes around 12 weeks. At the same time, the details for the packaging would be sent to the packaging company so that was ready before the silicon. The new timeline means that the packaging design has to be finished and booked 20 or more weeks before the final silicon design to ensure that the silicon and packaging come together at the right time.”

 

He went on to add that not being aware of this and planning accordingly could introduce a delay in the production of a chip by as much as 40 weeks.

 

As Sondrel offers a complete turnkey ASIC design and manufacturing service, the company spotted this growing problem in the supply chain a while back and has devised a solution to start the SoC package planning and design by assigning die bumps and assigning their x/y coordinates relative to the die corner.

 

Moving this stage to much earlier in the supply chain sequence avoids a massive and costly delay.

 

The bump locations are determined for each of the macros and PHYs as specified by the IP vendors using the floor plan and the SoC partitions’ locations.

 

For hard macros such as PCIe, HDMI and others, the bumps locations are specified by their relative offset from the macro corner whereas in soft macros (e.g., DDR), it is based on a certain pattern and a minimum pitch used in the bump assignment.