Etron and Lattice develop AI+DRAM platform

Author: EIS Release Date: Feb 24, 2020

 

Taiwanese DRAM design specialist Etron Technology has joined Lattice Semiconductor to  develop a miniaturised AI+DRAM platform for applications to terminal edge computing, industrial robots, and multimedia such as AR/VR, says Digitimes.

 

The platform contains Etron’s newly developed RPC (Reduced Pin Count) DRAM architecture (pictured) which has x16 DDR3 – LPDDR3 bandwidth but uses only 22 switching signals in a 40 ball FI-WLCS package.

 

That is combined with Lattice’s EPC 5 FPGA  to enable a miniaturized endpoint AI subsystem for high volume, form factor constrained applications.

 

 Etron’s RPC DRAM uses only 24 IO pins but is able to achieve the same bandwidth as x16 DDR3, and its WLCSP 256Mb DRAM package enables the miniaturization required in many applications.