DAC – where RISC-V thrives and mixed signal design blends in
Author: EIS Release Date: Aug 17, 2022
RISC-V and mixed signal design were strong themes from this year’s DAC in San Francisco, reports Caroline Hayes.
Golden Gate Bridge, San Francisco, California USA.
At last month’s 59th DAC (Design Automation Conference), a significant announcement was made by Siemens Digital Industries Software. Acknowledging the growth of mixed signal design, and the complexities it brings, the company announced Symphony Pro, an extension to its Symphony suite of design tools.
Described as an intuitive debug tool, it caters to both analogue and digital next generation design, explained Sathishkumar Balasubramanian, head of product management and marketing, analogue mixed signal at Siemens EDA. It supports the analogue mixed signal standard announced by the Accellera Systems Initiative, the industry organisation for system level design, modelling and verification standards.
The Symphony Pro is designed to verify mixed signal SoCs, increasingly used in automotive imaging, the IoT and 5G, where the analogue signal chain is integrated with the digital front end in 5G massive MIMO radios, for example. Mixed signal SoCs are also used in digital RF sampling data converters in radar systems and in image sensors, where analogue pixel readout circuits are combined with digital image signal processing. In data centres mixed signal circuits are used to deliver PAM4 signalling to accommodate the increased data loads.
The Pro addition to the Symphony suite covers layer configuration, hierarchies, analogue and digital design and is fully configurable with the Symphony kernel.
It allows power-aware verification for when a designer needs to consider power “from architecture to implementation” said Balasubramanian. Increasingly, mixed signal designs need power management for multiple voltage domains to ensure all digital elements are inserted and verified in real time.
Symphony Pro interfaces with Siemens’ Questa visualiser and is compatible with the industry-standard Universal Verification Methodology and Unified Power Format driven low power techniques to accelerate the speed, ease of use, debug and automated verification of mixed signal debug, which is typically a manual process, pointed out Balasubramanian. The increased clock speeds of logic gates within analogue circuits have been a headache for designers because the high frequency bi-directional signal flow stretches the limits of manual debug. Siemens has extended the digital debug environment for the Symphony Pro Visualizer MS so that it allows designers to view the hierarchy Spice list in a single environment with views of the waveform, electrical, logic and real-time parameters for seamless debugging, analysis and automation, resulting in an increase in productivity by a factor of 10, said Siemens.
A key capability, said Balasubramanian, is a single cockpit, which integrates with Questa and that can trace connectivity.
IC verification
The company also announced an expansion to its Calibre IC physical verification tool, with RealTime Custom and RealTime Digital tools for design rule checking (DRC) in custom, analogue/mixed signal and digital designs. There is now the ability to automatically track DRC across multiple regions in RealTime Custom, the interface to Calibre analysis engines. This feature allows multiple edits that can be fixed, tracked and checked simultaneously.
In RealTime Digital, there is now the capability for in-design fill using Calibre Yield Enhancer SmartFill. Designers can get foundry sign-off within the design cockpit.
There is also a Calibre nmDRC-Recon model in Calibre RealTime Digital for automated analysis of immature and incomplete designs across blocks, macros and full chip layouts. The designer can methodically find and fix the physical layout earlier in the design and it also enables verification flow. Siemens has added the capability to flexibly “grey-box” out immature cells and blocks, but still check DRC for interfaces to adjacent blocks or upper-level metal. This suppresses nusiance DRC to accelerate and improve debug. Runtimes are up to 50% faster compared to nmDRC-Recon alone, said the company.
RISC-V development kit
Demonstrating the ubiquity of the IoT and embedded design, OpenHW Group, which encourages its hardware and software designer members to collaborate to develop open source IP tools and software, demonstrated the RISC-V-based Core-V MCU development kit.
Data Stream series. Interplay of horizontal light rays and technological elements to serve as background in projects on technology and science
It was used to emulate an array of weather station sensors located around the world using the Core-V MCU, the software development kit, IoT sensors and AWS (Amazon Web Services) to display local temperature readings on the Core-V NexysA7 board.
The development kit uses Ashling’s RiscFree, its Eclipse-CDT based integrated development environment and debugger. There is also a cross-platform Gnu compiler collection compiler by Embecosm, FreeRTOS real time OS and AWS IoT ExpressLink connectivity, using Espressif’s RISC-V-based Wi-Fi radio over the AWS IoT ExpressLink.
An early access manufacturing programme for the development kit is co-ordinated by GroupGets.
Still with RF design, Ansys has collaborated with TSMC for the N6RF design reference flow. Using Ansys’ multi-physics simulation tools (RaptorX, Exalton, VelceRF and Totem), it has been created to accelerate design times of RF chips based on the N6 process technology, and to reduce over-design, says Ansys. RaptorX and Ansys HFSS have been enhanced to accept TSMC’s encrypted technology files.
Design capabilities include in-design analysis of electromagnetic coupling and the layout synthesis of inductive circuit devices, such as coils and transmission lines, with support for circuit-under-inductor techniques to reduce the area of the RF design.
This last feature is relevant, says Ansys’ John Lee, because today’s system design is increasing the scope of multi-physics effects, which affect power, performance and area. The N6RF design reference flow allows the companies’ joint customers to simulate and model electromagnetic interactions on TSMC ICs.
The RVVI
OpenHW Core has adopted the open standard RVVI (RISC-V Verification Interface) for its Core-V projects. The common methodology for the key components of the testbench connects the RTL instruction trace and reference models in lock-step-compare comparisons.
RVVI can be adopted for designs with privilege modes, vector extensions, out-of-order pipelines, multi-threading, multi-hart, user-defined custom instructions and extensions. Expanding RVVI to include external components with a standards-based interface allows the reuse of components from the Open Virtual Platforms library of open source models. Testbenches with RVVI-compatible virtual peripherals can now be used to support RISC-V verification with system level testing of asynchronous interrupt and debug module events.
Hideki Sugimoto, CTO of embedded SoC developer Nsitexe, is enthusiastic for RVVI and what it means for the automotive market. “The verification requirements to achieve the ASIL-D safety requirement level of ISO 26262 with a processor-based design are extensive, however verification IP reuse through standards such as RVVI help improve efficiency and achieve time to market schedules with all the design innovations that RISC-V enables,” he says.
Accellera’s analogue mixed signal guide
Accellera published the SystemC Analog/Mixed-Signal User’s Guide in 2020, in response to the growing trend for “tighter interaction between embedded hardware/software (HW/SW) systems and their analogue physical environment”. In sensor networks, image-sensing systems and cognitive radios, for example, all use digital HW/SW interwoven with analogue and mixed signal blocks such as RF interfaces, power electronics, sensors and actuators in heterogeneous systems.
The TSMC N6RF Design Reference Flow uses the Ansys multiphysics simulation platform to provide a low-risk and proven solution for designing radio-frequency chips
Understanding the interaction between HW/SW and the analogue and mixed signal subsystems at the architectural level requires a new modelling and simulation method, advises Accellera. SystemC supports HW/SW systems down to cycle-accurate behaviour through event simulation but the simulation kernel was not designed for analogue/continuous-time system modelling and simulation and does not support a refinement methodology to describe analogue behaviour from a functional level down to the implementation level. Analogue/mixed signal (AMS) extensions based on SystemC provide a uniform and standardised methodology for modelling heterogeneous AMS/HW/SW systems. They are built on top of the SystemC language standard IEEE Std. 1666-2011 and introduce execution semantics and system-level modelling methodologies to design and verify mixed signal systems. These AMS extensions can be used for executable specification, virtual prototyping, architecture exploration and integration validation.