Marvell’s 3nm platform

Author: EIS Release Date: Nov 1, 2022

Marvell has come up with its 3nm platform for cloud infrastructure ICs fabbed on TSMC processes.

 

3nm silicon from Marvell  includes long reach SerDes, PCIe Gen6 PHY, and several standards-based die-to-die interconnect technologies for managing data flow across the data infrastructure.

 

The IP portfolio is compatible with 2.5D packaging technologies such as TSMC’s  2.5D Chip-on-Wafer-on-Substrate (CoWoS) and will enable Marvell to develop multi-die, multi-chiplet SiP for its infrastructure products and co-development of custom ASICs.

 

Marvell’s  range of standard products for cloud infrastructure includes electro-optics, processors, accelerators, optical modules, Ethernet switches, storage controllers and PHY chips, and customised products through Marvell’s ASIC portfolio.

 

By developing and validating each of the critical IP blocks in silicon early in the availability of the 3nm process, Marvell can accelerate customers’ time-to-market while reducing the design risk and verification efforts associated with its complex monolithic or multi-die SoC designs