Lowering the power draw of embedded SRAM

Author: EIS Release Date: Nov 8, 2022

The power used by on-chip embedded SRAM has been growing in line with the feature set and is now a significant contributor to system power demand, states sureCore the Sheffield embedded SRAM developber.

 

Selecting off-the-shelf SRAM, which is often not optimised for power, does nothing to drive power efficiency.

 

sureCore is encouraging designers to consider the power profile of their embedded memory needs and look to both low voltage and low dynamic power solutions.

 

“Designers of power sensitive products have already made the shift to Bluetooth Low Energy from Classic Bluetooth as this uses a fraction of the power,” says sureCore CEO Paul Wells, “however few realise that using our ultra-low power embedded memory IP can offer similar significant reductions in power of up to 50%.””

 

“These wearable designs integrate a lot of memory to support all the sophisticated features and that plays an important part in the overall system power budget,” says Wells, “halving the memory power consumption can make all the difference to realising a competitive recharge cycle”sureCore has a range of power-optimised, standard products that deliver market-leading power profiles so urgently needed by these applications. mm

 

These include Everon, PowerMiser, and MiniMiser.

 

Further details can be found on sureCore’s product page.

 

Power savings can be realised both at nominal operating voltages and, increasingly importantly, at low to near threshold voltages allowing the application designers to tailor the power profile to the performance requirements.sureCore memories offer single rail, low voltage operation thereby allowing direct logic connection and hence significantly easing system level design considerations.

 

For those developers seeking to deliver genuinely market leading power performance, sureCore, as part of its bespoke custom memory development service, sureFIT, delivers memory sub-system solutions optimised for the three-dimensional design space of Power, Performance and Area (PPA). Such a solution provides the opportunity to engineer the optimal memory implementation for the target application.