While digital on-die point-of-load converters are trending, analogue designs are far from finished. Digital low-dropout (DLDO) regulators appeared a few years ago and looked to be the future for on‑die point‑of‑load regulators on digital chips (see ISSCC 2020 DLDOs further down).

However, a team at Seoul National University has turned the tables with a novel agile analogue LDO that offers high performance from limited space on 40nm CMOS.

According to the university’s ISSCC 2020 presentation: “DLDOs are commonly used in low‑power system‑on‑chips (SoCs) because of their low-voltage operation and fast transient response via the digital control of a power gate.

“However, the digital control of the power gate results in an output voltage ripple and a decrease in the power supply rejection. In addition, the transient performance of DLDOs depends strongly on the operating clock frequency.”

Its response is an analogue signal chain using simple two‑transistor CMOS inverters (five of the six triangles in the diagram, plus two hidden) to provide gain, and using an auto‑zero technique to boost accuracy in the error amplifier.

To keep the error amplifier operating continuously despite auto‑zeroing, two identical amplifiers are operated in parallel (one shown in diagram). While one is auto‑zeroing, the other is providing the signal path.

Subtle timings in the four clock signals that feed these paralleled error amplifiers mean that their output switches smoothly between exchange duties with a 50:50 duty cycle, while the internal auto‑zero switches take over just after the off‑duty amplifier has relinquished signal chain access, and then let go just before the amplifier takes up its responsibility again.

While the auto‑zero amplifiers have good dc and low‑frequency characteristics, they cannot respond to fast input voltage variations.

A particular problem is input rail changes that twitch the supply terminal of the inverter/amplifiers causing instant shifts in input offset voltage.

To tackle this, assistive inverter/amplifiers have been added, built as replicas of the main signal path amplifiers so that their offset changes track those in the main signal path amplifiers – even though the absolute offset value might differ.

Their outputs are ac‑coupled into the signal path in such a way as to cancel the effect of rail‑injected offset changes – pushing power supply rejection above the auto‑zero frequency.

Even at 30MHz there is 10dB of power supply ripple rejection.

Next in the main signal path is a slightly different inverter/amplifier: one with four instead of two mosfets – a p‑channel cascode pair on the high side and a n‑channel cascode pair on the low side.

“The second‑stage cascode inverter not only improves the loop gain by boosting its output impedance, but also reduces the quiescent current,” according to the ISSCC presentation.

In parallel with this are two transient detectors, implemented by changing one transistor in the inverter for a high‑threshold device – on the low side in one path (first inverter of the two‑inverter path) and on the high‑side in the other path. This has the effect of moving the threshold voltage of the paths up or down – represented by offset voltages in the diagram – creating auxiliary signal paths that only come into play when the error signal gets properly out‑of‑shape.

Undershoots cause the main power transistor to be turned on harder, while over‑shoots cause a transistor to pull the output down directly. Between these two thresholds, the loop operates normally without assistance.

At an input voltage of 0.4V and Vref of 0.35V, the LDO achieves 78mV droop settling in 500ns to a 1.04mA/10ns load step.

With 1V at the input and 0.9Vref, a step of 200mA/10ns is dealt with in 25ns, drooping 45mV.

Over 100mA can be supported from inputs above 700mV with only 50mV drop-out, and almost 40mA can be supplied from 350mV with the same 50mV drop-out.

At peak efficiency, 99.96% of input current is delivered to the load. Active area is 0.0057mm2, working out to >70A/mm²

Digital LDOs at ISSCC 2020

In digital LDOs (DDLOs) the crucial series pass transistor is replaced by many parallel‑connected p‑channel mosfets, each with its own RDSon.

As more current is required at the output, more and more of these mosfets are turned on to reduce the total series resistance.

The ingenuity lies in controlling which mosfets are used at any moment to get the best regulation.

At ISSCC this year Intel is presenting a synthesisable zero‑analogue DLDO for 10nm CMOS, for loads between 28mA and 2.74A that delivers up to 98.6% of input current to the output.

To sense the output voltage digitally, the natural slowing of inverters with supply voltage is exploited by analysing signals passing down a string of inverters.

The actual technique used is elaborate and thorough, allowing for process and temperature variations. After sensing, the signal path includes a digital PID controller, and the output uses 1,023 parallel transistors.

The whole thing fits into 0.0144mm² and no external capacitor is needed.

Seoul National University is describing a synthesisable 28nm DLDO that uses analogue comparitors made from repurposed digital NAND gates, exploiting their voltage/time response in a different way compared with Intel.

A fine loop with 63 small output transistors operates full time, then when the error voltage gets too high or too low, a coarse loop switches one of 64 larger transistors out or in.

Measurements indicate a 112mV voltage droop for a 430mA load‑current step with a 2ns rise time.

The whole thing fits into 0.049mm² and does not need external capacitors.

Rice University has not only created a DLDO, but used its step‑by‑step output switching nature as a way to foil voltage‑based side‑channel hacking attacks – where chip voltage is monitored during close‑up attacks to reduce time‑to‑cracking.

“Employing regulators for side‑channel attack defence is promising because they are already used in most systems and require no modifications to existing computing architectures and algorithms like other circuit-level defences”, according to the presentation.

At the same time as being a 65nm (0.018mm²) DLDO, the regulator boosts side‑channel attack resistance by 14,000 times on a 128-bit AES encryption engine, with negligible area, power or performance overhead compared the same AES design with a straight DLDO.

• Paper 32.4 A 0.4-to-1.2V 0.0057mm2 55fs‑transient‑FoM ring‑amplifier‑based low‑dropout regulator with replica‑based PSR enhancement.
• Paper 25.1 A fully synthesizable distributed and scalable all‑digital LDO in 10nm CMOS.
• Paper 25.2 A 480mA output‑capacitor‑free synthesizable digital LDO using CMP‑triggered oscillator and droop detector with 99.99% current efficiency, 1.3ns response time, and 9.8A/mm² current density.
• Paper 25.3 A 65nm edge‑chasing quantizer‑based digital LDO featuring 4.58ps‑FoM and side-channel-attack resistance.