Backside power delivery, which Intel calls PowerVia, is going to be a big factor in the company’s 20A node due in 2024. 

Backside power delivery, which Intel calls PowerVia, is going to be a big factor in the company’s 20A node due in 2024. 

Putting the power circuitry on the back of the wafer, reduces the area required  for front-side logic circuitry by up to 20%.

That means the process used for the interconnect layers can be relaxed and that, says Intel vp Ben Sell, “more than offsets the cost of this whole process.”

With separated and fatter wires for power and interconnection, “you get better power delivery and you get better signal wiring” says Sell, while the new  process is actually cheaper than the old one.

 

Intel used backside power delivery in a test chip based on the E-core which will be used in its  Meteor Lake  processor and found that: “The Intel E-core designed with PowerVia demonstrates >5% frequency improvement and>90% cell density with acceptable debug times as Intel 4.”

TSMC’s first use of backside power delivery will be in an N2 process due in H2 2025. TSMC says the technology improves speed by more than 10-12% and reduces the frontside area required for logic by 10-15%.

Intel says that its 18A process, using PowerVia, will be available to its foundry customers in 2024.  

The first product on the market to use PowerVia will come next year in the form of Arrow Lake, a PC  processor for using the  20A process.