ISSCC, the International Solid-state circuits conference, is the IEEE’s annual showcase for all that is best in on-chip circuit design from across the globe. Thousands of engineers will flock there this week to see hundreds of papers presented on subjects as diverse as picowatt radios and a 0.6Pflop AI processor.

IEEE National Cheng Kung University ISSCC2025 Paper3 audio amplifier
National Cheng Kung University of Taiwan presented a 1.6W audio power amplifier with a 121.3dB dynamic range and 115dB PSNR – high end audio performance to say the least.

It runs from 2.5 to 4.2V – not enough to deliver the necessary power into the intended 8Ω load.

IEEE National Cheng Kung University ISSCC2025 Paper3 audio amplifier

Rather than having an external boost converter to produce enough volts, this design adds just two mosfets and an inductor to the Class-D output structure (see diagram) to make it self-boosting for signal peaks.

Boosting is up to 2x, although output was limited to 5.5V peak, which is the limit of the output transistors.

Overall power efficiency is 87%, rather than an estimated 80% if a separate boost converter was used.

Operating the preceding signal conditioning at low voltage increases the challenge if high dynamic and high signal-to-noise are important.

This amplifier uses a capacitively coupled chopper-amplifier architecture, with capacitive feedback instead of resistive feedback to eliminates the thermal noise, and the chopping helping to mitigating flicker noise and improve power supply rejection.

Power supply rejection was 100dB at 217Hz and 76.1dB at 20kHz.

With a 4.2V, the amplifier was also tested with an 4Ω load where it delivered 2.44W at 1%THD+N.

Digital processing in this proof-of-concept is in an external FPGA which takes in 24bit 48kHz digital audio and produces 384kHz digital signals suitable for the analogue section shown.

Fabricated on a 0.5μm process, the analogue and power circuitry occupied 5.52mm2.

In the same ISSCC session, Tsinghua University and TU Delft presented a precision op-amp that achieved ±5.8μV input offset without using chopping or auto-zeroing.

Instead it uses two-temperature trimming during manufacture, but using an on-die heater instead of an external oven. The support circuitry included allows re-trimming in the field should this be deemed necessary.

Trimming starts two seconds after that heater is energised and takes ~20ms.

Implemented in 0.18μm CMOS, trimming after packaging achieved ±5.8μV room temperature offset with a drift of ±88nV/°C over -40 to 125°C.

In normal operating, the amplifier consumes 1.6mW from a 1.8V supply and occupies 0.14mm2.

 

ISSCC 2025 Paper 3.1
A 121.3dB-DR, 115dB-PSNR, digital-input capacitive-feedback Class-D audio aAmplifier with double-sided voltage-boosting (DSVB) modulation

ISSCC 2025 Paper 3.4
A CMOS operational amplifier achieving ±5.8μV 3σ offset and ±88nV/°C 3σ offset drift using an on-chip heater-based self-trimming technique