The IEEE’s International Solid-State Circuit Conference in San Francisco featured an overview of next-generation high-performance CPUs.

AMD revealed aspects of Zen 5, its x86-64 microprocessor for desktops and laptops.

Built on TSMC’s 4nm FinFET process, the 55mm2 eight cores have a total of 8.6bn transistors. Each core has a 1Mbyte private L2 cache and there is 32Mbyte of shared L3.

It gets around 16% more instructions per cycle compared with the Zen4, operates up to 5.7GHz and supports configurable 256 and 512 wide floating point data paths.

IBM described its 5.5GHz Telum II processor which has an enhanced AI accelerator and new data processing unit for I/O off-load.

Its 5nm 600mm2 die is made by Samsung, and has 43 billion transistors delivering a 40% up-lift in L2 cache, 36% more x-bus and on-chip voltage control, all with only a 5% power increase over of the previous generation.

An aside is was revealed that the 18 layers of metallisation implement over 24 miles of wiring and 165 billion vias.

Intel presented the I-O die of its Granite Rapids-D sixth-generation Xeon processor, intended to be integrated alongside one or more memory-inclusive processor dies.

The I-O die includes 200Gbit/s Ethernet, 32 lanes of 32Gbit/s PCIe5 and 16 lanes of PCIe4.

These interfaces are backed by on-die accelerators including 200Gbit/s look-aside crypto, 80Gbit/s compression, 160Gbit/s decompression and an accelerator for boosting vRAN and forward-error correction.

ISSCC25 p2.4 Intel chiplet processor 604In a second presentation, Intel went on to described 2.5D multi-die packaging for up to 20 chiplets on a 22 x 19mm passive silicon substrate – the latter made by UMC on a 130nm process.

The silicon substrate finally sits on a more conventional BGA substrate which provides yet another level of connectivity.

The chiplet slots are configured to allow various combinations of processor chiplets (16nm Tensilica LX7 by TSMC) and memory chiplets (4nm Intel) to be assembled depending on the intended application. Both chiplet options have AI processing capability: 2Top/s on the processor and 8Top/s on the memory (both INT8).

The scheme can accommodate larger chiplets that sit over two or four of the chiplet slots.

Several AI video processors were featured, including a 16nm convolutional neural network processor from National Tsing Hua University and the Taiwan Semiconductor Research Institute.

This processor is aimed at small-object detection and achieves 5.7Top/s on 896 x 896 26.6frame/s inputs, while consuming 1.37W from 1.09V.

Tsinghua University’s AI video processor turned to ‘3D Gaussian splatting’ processing to circumvent the frequent sampling and intensive network inference of traditional ‘neural radiance field’ processing, according to the presentation.

It is shape-aware, switching between a fast pipeline and a detailed pipeline.

The resulting 28nm CMOS chip achieves 6.65Top/s/W (peak) at 150MHz from 0.65V.

Korean research lab KAIST also turned to Gaussian splatting for its 28nm 3D image processor, this one surface-aware to allow it to usefully re-configure.

Other papers in this session described a 4K 210frame/s image signal processor from National Taiwan University and Google (40nm, 6.8mm2), an 8K 60frame/s neural-network processor from National Tsing Hua University and TSMC (16nm, 8mm2) and a 1K 107frame/s processor (22nm, 6mm2) for mobiles from Fudan University that can work for 0.52mJ/frame.