JEDEC and OCP (Open Compute Project Foundation) announce new Chiplet Design Kits for EDA use covering four areas: Assembly, Substrate, Material and Test.

JEDEC, OCP design kits progress automated SiP design using chiplets

Basically, they are a way for chiplet builders to provide – electronically – a standardised chiplet part description to customers. The idea is to pave the way for automating System-in-Package (SiP) design and build using such chiplets.

As mentioned, the four kits are the result of an alliance between the JEDEC Solid State Technology Association OCP’s Open Chiplet Economy Project. The included schemas are now part of the Global World Wide Standard JEDEC JEP30: Part Model Guidelines, they highlight.

Note, all schema files are digitally signed to ensure integrity when shared between a chiplet buyer and seller.

The kits can be found, respectively, here: Assembly, Substrate, Material and Test.

The releases build on earlier joint efforts to integrate the OCP Chiplet Data Extensible Markup Language (CDXML) specification into those Guidelines.

Material Design
For example, the Material Design Kit provides a framework for defining and validating the material properties and parameters required for SiP design.

It addresses elements such as substrates, interposers, redistribution layers and 3D integration technologies. And the material properties covered include dielectric constants, thermal conductivity and mechanical strength.

SiP design
“The new design kits, developed through collaboration between OCP and JEDEC, promote innovation in SiP design by fostering collaboration and openness, ensuring broad accessibility, and supporting rapid adoption across the semiconductor industry,” said said James Wong, Chair of the JEDEC JEP30 Task Group.

“These kits promote openness, streamline design workflows, and reduce manual interventions, thereby significantly improving design efficiency, scalability, and innovation.”

Leading-edge nodes
“Chiplets have rapidly become the efficient and cost-effective way to develop chips at leading-edge nodes, and have been used successfully to improve SiP performance with cost efficiencies at scale, because the entire chip development cycle is managed in-house at large companies,” said said Cliff Grossner, Ph.D., Chief Innovation Officer at the Open Compute Project Foundation.

“To provide an open environment where designers drop known-good third-party sourced Chiplets into their designs requires the development of an open marketplace. Recently the OCP took the next step in establishing an Open Chiplet Economy with the opening of the OCP Chiplet Marketplace.”

Design kits
The schemas included in the kits have been designed, say the organisations, to scale to a very large number of chiplet interconnection points, while also keeping the schema size manageable.

“There are still many opportunities to create additional standardization efforts bringing together JEDEC’s strength in setting global standards for the microelectronics industry with OCP’s expertise in specifying system level devices seeding emerging technologies and markets,” said John Kelly, President, JEDEC. “JEDEC is delighted with this next step in the collaboration with OCP moving the market forward.”