Menlo Micro announced an 80Gbit/s PAM4 loop-back switch for testing asymmetric SerDes busses at IMS 2025, the International Microwave Symposium in San Francisco.

Menlo MM5625 80Gbit/s PAM4 loop-back switch
“MM5625 delivers over 100 different configurations for the most complex SerDes bus test challenges,” according to the company. It can “support the high-speed differential signal switching required in the latest PCIe Gen 5, Gen 6, and other standards”.

There are 12 channels and 128 possible control states, compared with 16 states for the company’s earlier products.

Bandwidth is dc to 20GHz range, with -2.7dB insertion loss at 20GHz and built-in dc-blocking capacitors.

A host processor is required, controlling though an SPI bus – several devices can be daisy-chained on the same bus.

Recommended supplies are 5V for the charge pump, 3.3V for logic and up to 5.5V for the IO interface.

“MM5625 is not intended for hot switching applications and care should be taken to insure that switching occurs at less than 0.5 V,” warned the company. “Further, the voltage at the switch terminals must be within ±0.5V relative to signal ground – RF pins must not be allowed to electrically float during switch operation and therefore require some form of DC path to ground to prevent charge accumulation.”

Packaging is 8.2 x 8.2 m LGA, and an integrated charge pump driver removes the need for external biasing circuitry.

Menlo MM5625 80Gbit/s PAM4 loop-back switch

Durability is “Greater than three billion switching operations”, said Menlo.

Use is expected in wafer sorting and test equipment for data centre chips including processors, re-timers and memories.