Pathfinding-PDKs (P-PDKs) will restore academia to the forefront of process technology innovation, says imec.

Ever since the 20-nanometer node, scaling has been enhanced by introducing architectures such as FinFETs, nanosheets, forksheets, CFETs, and novel integration solutions such as 3D stacking and chiplet integration. 

These shifts transformed chip design into a process of design-technology co-optimization (DTCO) and even system-technology co-optimization (STCO).

But as industry raced towards these angstrom nodes, where we’re no longer just shrinking transistors, but rewriting the chip architecture, academic research gradually fell behind. 

When the complexity of semiconductor design increased, traditional abstraction layers, which had long enabled universities to explore realistic design scenarios, no longer matched the complexity of advanced technologies. 

As a result, university research gradually drifted away from industrial practice, cutting academic researchers off from driving innovation.

That’s about to change with pathfinding process design kits (P-PDKs). P-PDKs: will put academia back into the semiconductor fast lane.

What sets P-PDKs apart is that they anticipate future technologies. They’re built on predictive models of upcoming technologies.

This allows researchers to explore system-level trade-offs, assess architectural implications, and prepare design flows before the technology reaches maturity, giving innovators, including university researchers, a crucial head start in designing for the next wave of chips.

“When it comes to beyond-2nm semiconductor P-PDKs to restore academia’s role in process developmentinnovation, you can’t tape out a physical circuit, because the technology simply doesn’t exist yet,” Anita Farokhnejad (pictured) DTCO Program Manager at imec. “but you can already explore what the performance will look like, what the system implications are and how to prepare architecture and design flows for what’s coming.”

To support this forward-looking exploration, NanoIC’s P-PDKs are grounded in imec’s 2nm process flows. From this, detailed 3D device structures are modelled and abstracted into compact models for circuit-level simulation. 

These enable full standard cell libraries, along with predictive transistor models, interconnect stack definitions, parasitic parameters, design rule files (DRC, LVS), and reference design examples. 

The result: access to a complete design environment and a feedback loop that connects design insights back to technology development.

Accelerating a next-generation semiconductor ecosystem

With the first P-PDK released in 2024 (2nm), and the second coming up in November 2025, access to the P-PDKs is about more than providing early-stage design kits.

 By serving as a bridge between process innovation and system design, the NanoIC pilot line ensures that the future of compute isn’t shaped behind closed doors but developed in an ecosystem that includes the academic minds best equipped to explore bold new design paradigms.

The introduction of pathfinding PDKs is therefore more than a technical advance. It restores alignment between academic research and industrial practice. Universities can now align their exploration of bold new architectures with advanced technology benchmarks, while industry benefits from disruptive ideas developed in close connection to realistic technology paths.