LeapMind, the eight year-old Tokyo AI startup, showed the results of the performance estimations conducted on its AI inference accelerator at last week’s  COOL Chips 23 event in Tokyo.

The implementation of the ASIC design flow was carried out with Taiwan’s Alchip Technologies.

Since deep learning technology generally requires a significant amount of computing resources, its practical applications in edge devices are affected by power, accuracy, and speed:

Power must be saved owing to the limited supply of power, e.g., battery drive being limited or heat radiation being limited by casing size.

The technology must be lightweight so that the memory mounted on the edge device can process data while maintaining trained AI model accuracy.

Inference processing must be speedy because there is a control target that awaits and uses the inference results.

LeapMind’s core technology, called “extreme quantisation technology”, operates at both software and hardware levels with a network optimised for practical applications and a dedicated compiler.

The results of these technological developments thus far were presented in the form of performance estimation values.

These performance estimations confirmed that LeapMind’s technology can be expected to be effective  for both FPGAs and ASICs.

When the PPA (Power, Performance, and Area) estimations were conducted, which are indices for performance when mounted on silicon, Alchip, along with LeapMind, examined and conducted a series of layout trials on multiple memory configurations.

The results of the conducted power simulations, which followed the set layout and wiring, confirmed LeapMind’s PPA predictions:

Considering that these performance estimations did not use any special cell library or memory, nor any power-saving methods of implementation, there is still room for improving power efficiency at the implementation stage.

Further reductions of power by using clock gating techniques and an effective division of area to account for multiple power supply voltages are possible.

Since the accelerator can be adapted for feature re-extraction for use under ultra-low voltage conditions, greater performance improvements can be expected in actual use with ASIC technology.