Imperas Software, the virtual platforms and software simulation specialist, today announced that Mellanox Technologies has selected the Imperas advanced hardware verification of RISC-V processors.

RISC-V, as an open ISA, permits many configuration and options for processor implementation and microarchitectural features, in addition to extension with custom instructions. Simulation based methodologies are the foundation for hardware design verification (DV) throughout the semiconductor industry in achieving first pass prototype success.

The Imperas RISC-V models are provided in source form, which allows users to adapt and extend for custom configurations independently. The model can be encapsulated in a UVM environment for a complete SystemVerilog DV flow.

By using the RISC-V reference model in a side-by-side configuration with the target RTL, it is possible to run step-and-compare analysis either interactively or in automated regression tests for continuous integration.

Typical processor verification plans include rigorous testing of the RTL with comparison to a golden reference model, using a range of stimulus inputs such as the RISC-V International Association Compliance suite, directed tests, and constrained random Instruction Stream Generator (ISG) tests, like the Google open-source project known as Google RISC-V DV-ISG.